133Fermer135
ZerosquareLe 13/06/2012 à 21:24
Le "mieux" que j'ai vu, c'est un modèle de PIC qui sautait aléatoirement des instructions cheeky (il y avait la probabilité d'occurence dans la doc, de mémoire à 4 MHz elle était quasi-nulle, mais non négligeable à 20 MHz ; mais je ne me souviens plus de la référence).

Sinon, en prenant un errata au hasard (honnêtement, j'en ai pris un au pif sur Google) :
1. Doze Mode
When Doze mode is enabled, any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle.

2. 12-bit Analog-to-Digital Converter (ADC) Module
For this revision of silicon, the 12-bit ADC module INL, DNL and signal acquisition time parameters are not within the published data sheet specifications.

3. 10-bit ADC Module
For this revision of silicon, the 10-bit ADC module DNL, conversion speed and signal acquisition time parameters are not within the published data sheet specifications.

4. DMA Module: Interaction with EXCH Instruction
The EXCH instruction does not execute correctly when one of the operands contains a value equal to the address of the DMAC SFRs.

5. DISI Instruction
The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero.

6. Motor Control PWM
There is a glitch in the PWMxL signal in Single-Shot mode with complementary output. Another glitch occurs when resuming from a Fault condition in Free-Running mode with complementary output.

7. Output Compare Module
The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time.

8. Output Compare Module in PWM Mode
The output compare module will miss one compare event when the duty cycle register value is updated from 0x0000 to 0x0001.

9. SPI Module in Frame Master Mode
The SPI module will fail to generate frame synchronization pulses in Frame Master mode if FRMDLY = 1.

10. SPI Module in Slave Select Mode
The SPI module Slave Select functionality will not work correctly.

11. SPI Module
The SMP bit does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode.

12. ECAN™ Module
ECAN transmissions may be incorrect if multiple transmit buffers are simultaneously queued for transmission.

13. ECAN Module
Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer ID register.

14. ECAN Module Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode.

15. I2C™ Module
The Bus Collision Status bit does not get set when a bus collision occurs during a Restart or Stop event.

16. INT0, ADC and Sleep/Idle Mode
ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero.

17. Doze Mode and Traps
The address error trap, stack error trap, math error trap and DMA error trap will not wake-up a device from Doze mode.

18. JTAG Programming
JTAG programming does not work.

19. UART
With the parity option enabled, a parity error may occur if the Baud Rate Generator (BRG) contains an odd value.

20. UART
The Receive Buffer Overrun Error Status bit may get set before the UART FIFO has overflowed.

21. UART
UART receptions may be corrupted if the BRG is set up for 4x mode.

22. UART
The UTXISEL0 bit is always read back as zero.

23. UART
The auto-baud feature may not calculate the correct baud rate when the BRG is set up for 4x mode.

24. UART
With the auto-baud feature selected, the sync break character (0x55) may be loaded into the FIFO as data.

25. ECAN Module
Buffers 6 and 7 may intermittently transmit the wrong message type.

26. I2C Module
A write collision does not prevent the transmit register from being written.

27. I2C Module
The ACKSTAT bit only reflects the received ACK/NACK status for master transmissions, but not for slave transmissions.

28. I2C Module
The D_A Status bit does not get set on a slave write to the transmit register.

29. Traps and Idle Mode
If a clock failure occurs when the device is in Idle mode, the oscillator failure trap does not vector to the Trap Service Routine.

30. MCLR Wake-up from Sleep Mode
An MCLR wake-up from Sleep mode does not wait for the on-chip voltage regulator to power up.

31. ECAN Module
The C1RXOVF2 and C2RXOVF2 registers always read back as 0x0000.

32. FRC Oscillator
Internal FRC accuracy parameters are not within the published data sheet specifications.

33. Quadrature Encoder Interface (QEI) Module
The QEI module does not generate an interrupt in a particular overflow condition.

34. Device ID Register
The content of the Device ID register changes from the factory programmed value.

35. SPI
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is erroneously enabled by the SPI2 module.

36. UART
The auto-baud feature measures baud rate inaccurately for certain baud rate and clock speed combinations.

37. Motor Control PWM (Faults in Latched mode)
Subsequent faults in the same timer cycle are missed during a latched fault.

38. Motor Control PWM (Fault-driven Wake-up)
Fault-driven Wake-up from Idle does not function.

39. DMA Module
DMA data transfers that are active in Single-Shot mode while the device is in Sleep or Idle mode may result in more data transfers than expected.

40. Doze Mode and Traps A DMA error trap may not be generated when the device is in Doze mode.
Une bonne proportion sont des bugs graves (feature inutilisable, corruption ou perte de données, risque de comportement imprévisible).