[nosmile]Oh, les PIC18 ont aussi leurs bugs "sympas" :

1. Module: ECCP
When the ECCP module is operating in Half-Bridge mode, use of a dead-band delay other than zero will have the effect of introducing an unintended pulse on the P1A and P1B signals.

2. Module: I/O (Parallel Slave Port)
The Input Buffer Full Status bit, IBF, of the TRISE register (TRISE<7>) may be inadvertently cleared, even when the PORTE input buffer has not been read.

3. Module: Core (Program Memory Space)
Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the device’s rated temperature range (-40°C).

4. Module: Core (Program Memory Space)
Under certain conditions, the execution of a table read instruction may yield erroneous results. This has been observed when a table read instruction and its read destination, as indicated by the Table Pointer registers, are on opposite sides of the 4000h program memory address boundary.

5. Module: Core (Program Memory Space)
Under certain conditions, the execution of some control operations may yield unexpected results. This has been observed when the following instructions vector code execution across the 4000h program memory address boundary:
• CALL
• GOTO
• RETURN
• RETLW
• RETFIE

6. Module: Data EEPROM
When reading the data EEPROM, the contents of the EEDATA register may be corrupted if the RD bit (EECON1<0>) is set immediately following a write to the address byte (EEADR). The actual contents of the data EEPROM remain unaffected.

7. Module: A/D (External Voltage Reference) and Comparator Voltage Reference
When the external voltage reference, VREF-, is selected for use with either the A/D or comparator voltage reference, AVSS is connected to VREF- in the comparator module. If VREF- is a voltage other than AVSS (which must be tied externally to VSS), excessive current will flow into the VREF- pin.

8. Module: CAN
CAN Disable mode change request is not confirmed. A CAN Disable mode request by writing ‘001’ to the REQOP bits (CANCON<7:5>) immediately changes the OPMODE bits (CANSTAT<7:5>), implying that Disable mode is accepted. This occurs even though the CAN module itself may not have switched its state.

9. Module: MSSP (All I2C™ and SPI™ Modes)
The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read.

10. Module: MSSP (SPI, Slave Mode)
In its current implementation, the SS (Slave Select) control signal generated by an external master processor may not be successfully recognized by the PIC® microcontroller operating in Slave Select mode (SSPM3SPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall times) are more likely to be missed than than slower transitions.

11. Module: CAN
An incoming CAN message may not be saved properly to a CAN receive buffer if one of the following conditions is met:
1. Bank 15 is selected and the firmware attempts to read RXB0 or RXB1 registers while a CAN message reception is in progress.
2. Bank 15 is selected and an instruction is executed whose lower 8 bits match with one of the CAN receive buffer addresses (RXBn addresses in the range of 0xF61 to 0xF6E and 0xF51 to 0xF5D) while a CAN message reception is in progress. Some of the instruction examples are:
• 0xFF68 (NOP)
• 0xEE68 (first half of GOTO 0xD0)
• 0x0E6A (MOVLW 0x6A)
• 0x6055 (MOVF 0xF66, W)
Other instruction combinations exist.
3. The firmware attempts to access GPR (General Purpose Register) addresses between addresses 0x51 and 0x5D in the Access Bank while a CAN message reception is in progress. Some of the instruction examples are:
• MOVWF 0x57, A
• ADDWF 0x57, A
• MOVF 0x57, W, A

12. Module: Reset
It has been observed that in certain Reset conditions, including power-up, the first GOTO instruction at address 0x0000 may not be executed. This occurrence is rare and affects very few applications.

13. Module: CANUnder specific conditions, the first five bits of a transmitted identifier may not match the value in the Transmit Buffer ID register, TXBxSIDH. If the CAN peripheral detects a Start-of-Frame (SOF) in the third bit of interframe space, and if a message to be transmitted is pending, the first five bits of the transmitted identifier may be corrupted.