I was researching deeper into this yesterday , and it seems that the order of the read/write cycles in a MOVE.L (a0)+,(a1) instruction is probably :

Read (4 cycles), Read (4 cycles), Write (4 cycles), Write (4 cycles) Read (4 cycles) = 20 cycles total

This seems counter intuitive e.g. Why is there a "Read" at the end? It's because the read at the end is a pre-fetch (the 68000 has a small 3 word prefetch queue). It's also possible one of the other reads is a prefetch too.

Assuming I am right (can anyone confirm?) - the 2nd example in my previous post should still work because there is still a 16 cycle delay between writing to the VRAM address port again.

68000 is more complicated that I thought. I had just assumed if the manual said 3 reads and 2 writes they would be sequential!


The info on pre-fetch comes from here : https://pasti.fxatari.com/68kdocs/68kPrefetch.html

MOVE instructions. Most variants, except the ones noted below

1) Perform as many prefetch cycles as extension words are in the source operand (optional).

2) Read source operand (optional if source is register).

3) Perform as many prefetch cycles as extension words are in the destination operand (optional).

4) Writes memory operand.

5) Perform last prefetch cycle.