Mon premier programme GP32 - Page 2

-------------------------------------------------------------------------------
0x00000000 - 0x0003ffff 512kb system rom (BOOT_ROM)

Exception Vectors

0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software Interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort
0x00000014 Reserved Reserved
0x00000018 IRQ IRQ
0x0000001C FIQ FIQ

-------------------------------------------------------------------------------
0x0c000000 - 0x0c7fffff 8mb workram (WORK_RAM)
0x0c780000 - 0x0c7fffff 0.5mb used by system
-------------------------------------------------------------------------------
0x14000000 - 0x15a0003f hardware registers

- The special registers have to be accessed by the recommended access unit.
- All registers except ADC registers, RTC registers and UART registers must be
read/written in word unit (32bit) at little endian.
- It is very important that the ADC registers, RTC registers and UART registers
be read/written by the specified access unit and the specified address.
Moreover, one must carefully consider which endian mode is used.

W: 32-bit register, access by LDR/STR or int type pointer(int *)
HW: 16-bit register, access by LDRH/STRH or short int type pointer(short int *)
B: 8-bit register, access by LDRB/STRB or char type pointer(char int *)
-------------------------------------------------------------------------------

MEMORY CONTROLLER

BWSCON 0x14000000 W r/w Bus Width & Wait Status Control
BANKCON0 0x14000004 Boot ROM Control
BANKCON1 0x14000008 BANK1 Control
BANKCON2 0x1400000c BANK2 Control
BANKCON3 0x14000010 BANK3 Control
BANKCON4 0x14000014 BANK4 Control
BANKCON5 0x14000018 BANK5 Control
BANKCON6 0x1400001c BANK6 Control
BANKCON7 0x14000020 BANK7 Control
REFRESH 0x14000024 DRAM/SDRAM Refresh Control
BANKSIZE 0x14000028 Flexible Bank Size
MRSRB6 0x1400002c Mode register set for SDRAM
MRSRB7 0x14000030 Mode register set for SDRAM

USB HOST CONTROLLER

HcRevision 0x14200000 W Control and Status Group
HcControl 0x14200004
HcCommonStatus 0x14200008
HcInterruptStatus 0x1420000c
HcInterruptEnable 0x14200010
HcInterruptDisable 0x14200014
HcHCCA 0x14200018 Memory Pointer Group
HcPeriodCuttentED 0x1420001c
HcControlHeadED 0x14200020
HcControlCurrentED 0x14200024
HcBulkHeadED 0x14200028
HcBulkCurrentED 0x1420002c
HcDoneHead 0x14200030
HcRmInterval 0x14200034 Frame Counter Group
HcFmRemaining 0x14200038
HcFmNumber 0x1420003c
HcPeriodicStart 0x14200040
HcLSThreshold 0x14200044
HcRhDescriptorA 0x14200048 Root Hub Group
HcRhDescriptorB 0x1420004c
HcRhStatus 0x14200050
HcRhPortStatus1 0x14200054
HcRhPortStatus2 0x14200058

INTERRUPT CONTROLLER

SRCPND 0x14400000 W R/W Interrupt Request Status
INTMOD 0x14400004 W Interrupt Mode Control
INTMSK 0x14400008 R/W Interrupt Mask Control
PRIORITY 0x1440000c W IRQ Priority Control
INTPND 0x14400010 R/W Interrupt Request Status
INTOFFSET 0x14400014 R Interrupt request source

DMA

DISRC0 0x14600000 W R/W DMA 0 Initial Source
DIDST0 0x14600004 DMA 0 Initial Destination
DCON0 0x14600008 DMA 0 Control
DSTAT0 0x1460000c R DMA 0 Count
DCSRC0 0x14600010 DMA 0 Current Source Address
DCDST0 0x14600014 DMA 0 Current Destination Address
DMASKTRIG0 0x14600018 R/W DMA 0 Mask Trigger
DISRC1 0x14600020 W R/W DMA 1 Initial Source
DIDST1 0x14600024 DMA 1 Initial Destination
DCON1 0x14600028 DMA 1 Control
DSTAT1 0x1460002c R DMA 1 Count
DCSRC1 0x14600030 DMA 1 Current Source Address
DCDST1 0x14600034 DMA 1 Current Destination Address
DMASKTRIG1 0x14600038 R/W DMA 1 Mask Trigger
DISRC2 0x14600040 W R/W DMA 2 Initial Source
DIDST2 0x14600044 DMA 2 Initial Destination
DCON2 0x14600048 DMA 2 Control
DSTAT2 0x1460004c R DMA 2 Count
DCSRC2 0x14600050 DMA 2 Current Source Address
DCDST2 0x14600054 DMA 2 Current Destination Address
DMASKTRIG2 0x14600058 R/W DMA 2 Mask Trigger
DISRC3 0x14600060 W R/W DMA 3 Initial Source
DIDST3 0x14600064 DMA 3 Initial Destination
DCON3 0x14600068 DMA 3 Control
DSTAT3 0x1460006c R DMA 3 Count
DCSRC3 0x14600060 DMA 3 Current Source Address
DCDST3 0x14600064 DMA 3 Current Destination Address
DMASKTRIG3 0x14600068 R/W DMA 3 Mask Trigger

CLOCK & POWER MANAGEMENT

LOCKTIME 0x14800000 W R/W PLL Lock Time Counter
MPLLCON 0x14800004 MPLL Control
UPLLCON 0x14800008 UPLL Control
CLKCON 0x1480000c Clock Generator Control
CLKSLOW 0x14800010 Slow Clock Control
CLKDIVN 0x14800014 Clock divider Control

LCD CONTROLLER

LCDCON1 0x14a00000 W R/W LCD Control 1
LCDCON2 0x14a00004 LCD Control 2
LCDCON3 0x14a00008 LCD Control 3
LCDCON4 0x14a0000c LCD Control 4
LCDCON5 0x14a00010 LCD Control 5
LCDSADDR1 0x14a00014 STN/TFT: Frame Buffer Start Address1
LCDSADDR2 0x14a00018 STN/TFT: Frame Buffer Start Address2
LCDSADDR3 0x14a0001c STN/TFT: Virtual Screen Address Set
REDLUT 0x14a00020 STN: Red Lookup Table
GREENLUT 0x14a00024 STN: Green Lookup Table
BLUELUT 0x14a00028 STN: Blue Lookup Table
DITHMODE 0x14a0004c STN: Dithering Mode
TPAL 0x14a00050 TFT: Temporary Palette

0x14A00400 palette memory
Palette format is 5:6:5 (or 5:5:5:1)
each entry is 32bit

UART

ULCON0 0x15000000 W R/W UART 0 Line Control
UCON0 0x15000004 UART 0 Control
UFCON0 0x15000008 UART 0 FIFO Control
UMCON0 0x1500000c UART 0 Modem Control
UTRSTAT0 0x15000010 R UART 0 Tx/Rx Status
UERSTAT0 0x15000014 UART 0 Rx Error Status
UFSTAT0 0x15000018 UART 0 FIFO Status
UMSTAT0 0x1500001c UART 0 Modem Status
UTXH0 0x15000020 B W UART 0 Transmission Hold
URXH0 0x15000024 R UART 0 Receive Buffer
UBRDIV0 0x15000028 W R/W UART 0 Baud Rate Divisor

ULCON1 0x15004000 W R/W UART 1 Line Control
UCON1 0x15004004 UART 1 Control
UFCON1 0x15004008 UART 1 FIFO Control
UMCON1 0x1500400c UART 1 Modem Control
UTRSTAT1 0x15004010 R UART 1 Tx/Rx Status
UERSTAT1 0x15004014 UART 1 Rx Error Status
UFSTAT1 0x15004018 UART 1 FIFO Status
UMSTAT1 0x1500401c UART 1 Modem Status
UTXH1 0x15004020 B W UART 1 Transmission Hold
URXH1 0x15004024 R UART 1 Receive Buffer
UBRDIV1 0x15004028 W R/W UART 1 Baud Rate Divisor