I read in the http://furrtek.free.fr/noclass/neogeo/mvstech.txt document that the P1.rom uses slower memory and that memory access takes an extra 2 mclks. I am confused as to when I should add this delay (when figuring out timings). Do I add it to all instructions - since they are stored in the P1 rom? or just to certain instructions?

It says : "All registers in the $3xxxxx range are accessible at full speed, even those used for VRAM I/O" so when am I accessing VRAM - does this mean I don't have to add extra cycles to my timings?

Also, am I correct that the 2 mclks delay = 1 CPU cycle?

Here it specifies (from mvstech.txt)
68000 Memory Map

/DTACK delay by region

000000-0FFFFF : 1-cycle delay (10 mclks/access)
100000-1FFFFF : Full speed (8 mclks/access)
200000-2FFFFF : Full speed (8 mclks/access)
300000-3FFFFF : Full speed (8 mclks/access)
400000-7FFFFF : Full speed (8 mclks/access)
800000-BFFFFF : 2-cycle delay (12 mclks/access)
C00000-CFFFFF : Full speed (8 mclks/access)
D00000-DFFFFF : Full speed (8 mclks/access)
E00000-FFFFFF : Full speed (8 mclks/access)

These delays enable use of slower memories. Only the program ROM area
and JEIDA card space are affected. All registers in the $3xxxxx range
are accessible at full speed, even those used for VRAM I/O.

Memory map, just a rough outline for now:

000000-0FFFFF : Cartridge P1 ROM
100000-1FFFFF : Work RAM (64K, mirrored every 64K)
200000-2FFFFF : Unused ($4E71)
300000-31FFFF : I/O port #1 *** $DFBF word of io ports / write to kick wdt
320000-33FFFF : I/O port #2 *** $3F1F/$3F5F
340000-35FFFF : I/O port #3 *** $FF71 read io
360000-37FFFF : Unused ($4E71)
380000-39FFFF : I/O port #4
3A0000-3BFFFF : Write to set system control latch / Read is unused ($4E71)
3C0000-3DFFFF : Video registers
3E0000-3FFFFF : Unused ($4E71)
400000-7FFFFF : Color RAM (8K bank, mirrored every 8K)
800000-BFFFFF : JEIDA card interface
C00000-CFFFFF : BIOS ROM (128K, mirorred every 128K)
D00000-DFFFFF : Save RAM (64K, mirrored every 64K)
E00000-FFFFFF : Unused ($4E71)

Thank you for any help


I looked into this a bit more and found this in the dev wiki

The 68k is able to wait for data by making it insert wait cycles during bus access. This allows the use of slow, cheaper memories.

The NeoGeo provides wait state generation for 3 memory zones:

000000~0FFFFF: ROM zone (P ROM) - Configurable, 0 or 1 cycle
200000~2FFFFF: PORT zone (P ROM or special chips) - Configurable, 0, 1, 2 or more cycles
800000~BFFFFF: Memory card - Fixed, 2 cycles

So it seems the game cartridge chooses a delay if it requires one? I use the puzzle de pon ROM with NeoDev kit to code. Do I need to worry about a delay on this? Or is it delay-free?